1. Field of the Invention
The present invention relates to a method and apparatus for protection switching based on memory control, and more particularly, to a protection switching apparatus and method for performing data path protection switching by hardware when a failure occurs in a data path for transmission and reception between packet transport systems.
2. Description of the Related Art
Due to popularization of the Internet, and wire-wireless Internet convergence, data traffic is gradually increased, which may lead to a limitation to acceptance of a high-quality service, for example an Internet Protocol Television (IPTV), to an existing packet transport system. Accordingly, schemes for various premium transmission services to provide an end-to-end Quality of Service (QoS) and scalability using a data link layer are being sought.
To provide high-quality premium transmission services, a stable operation may need to be performed, and an efficiency of a packet transport system may need to be maximized, despite a failure occurring in the packet transport system or a failure in a data path between packet transport systems. To provide high-quality premium transmission services between packet transport systems, protection switching, restoration, and the like may be used.
The protection switching may refer to a method of classifying paths between packet transport systems in a transport network into working paths and protection paths, of carrying traffic, that is, a data packet via a working path when no failure occurs, and of carrying traffic via a protection path based on control of an operator when a failure occurs in a network.
The restoration may refer to a method of restoring an interrupted service to an original service state, using resources and a path available in a network including packet transport systems.
Conventional protection switching between packet transport systems is performed using a general purpose processor, through communication between a packet processor, a host processor, and a main processor that is an upper layer processor. The packet processor, the host processor and the main processor may be mounted in each of a plurality of line cards of a packet transport system. The main processor may control the packet transport system. For example, the conventional protection switching may be performed on a path failure by processing an Operation, Administration and Maintenance (OAM) frame and an Automatic Protection Switching (APS) frame including protection switching protocol message information. In other words, an occurrence of the path failure may be recognized first by a hardware-based packet processor in a line card. However, a packet processor in a line card that detects the path failure may transmit a failure signal and event information to a host processor mounted in the line card and accordingly, protection switching may be performed based on software by protocol communication with the main processor.
As described above, the conventional protection switching may be processed in software with a relatively low speed based on a main processor of a packet transport system and a host processor in a plurality of line cards. Accordingly, when a failure occurs, a few hundreds of connections satisfying a time of about 50 milliseconds (ms) required for protection switching may be set as a maximum limit. Accordingly, Continuity Check (CC) and Connectivity Verification (CV) requiring real-time processing may not be efficiently performed, and a packet may be lost based on a situation of a path failure, which may result in a reduction in performance of a packet transport system.